In the previous chapter, we looked at what interrupts are and the role of the NVIC. Now, lets look at which interrupts are actually available on the RP2040.
Interrupts fall into two groups: system exceptions and external interrupts.
System exceptions are defined by the CPU architecture itself. These include reset and fault handlers. They behave the same way across most Cortex-M chips.
External interrupts come from peripherals on the RP2040. Each peripheral that can generate an interrupt has an IRQ number and a vector name. These are the names you will see in code.
The table below shows the external interrupts on the RP2040, numbered from 0 to 25. They cover common peripherals such as timers, GPIO, DMA, and communication interfaces like I2C, SPI, and UART.
You do not need to memorize this table. Its purpose is to help you recognize where names like I2C0_IRQ or UART0_IRQ come from when you see them in examples or documentation.
Important note: The RP2040 has two Cortex-M0+ cores, each with its own NVIC. On each core, only the lower 26 IRQ signals (0-25) are connected to hardware peripherals. IRQs 26-31 are not connected and will never fire.
In the next chapter, we will see how Embassy uses these interrupts without requiring you to write interrupt handlers manually.
The RP2040 has 26 external hardware interrupt lines (IRQ 0-25) connected to each core’s NVIC. IRQs 26-31 exist in the NVIC but are not connected to hardware peripherals and will never fire from hardware.